o 3-6 years experience in IC verification, including experience with constrained-random, coverage driven verification environments
o Experience developing and working with object oriented verification languages (Vera, Specman, System Verilog, VMM, OVM, UVM)
o A solid understanding of object-oriented concepts and experience designing class-based test benches
o Excellent written and oral communication skills
o Strong debugging skills
o Strong C/C++, Perl, and scripting skills
o Experience with formal verification tools, hardware design and debug, SystemC and other programming languages are a plus.
o Experience working with OVM, or Specman e is a plus