Evaluate and deploy the most efficient designs techniques for delivering increasingly complex IP / SoC designs within aggressive, market-driven schedules.
Own and Lead IP design through the concept till IP delivery and validation on Silicon.
Ensure quality adherence during all stages of the project life cycle. Also carry out a thorough analysis of existing processes, recommend and implement the process improvements to ensure Zero Defect designs.
Influencing and building technological innovations for self and in team environment.
Ability to work well as part of a team both locally, and also with remote or multi-site teams.
Self starter with 5-10 years of experience on IP design / Sub-system / SOC level multimillion Gate and complex Design with multiple clocks and power domains - with minimal supervision.
Graphics/Multimedia/ Networking protocols like Ethernet, USB, ITU T.656, Serial Protocols deeper understanding in one or more domains.
Experience in automotive protocols like LIN, CAN, Flexray would be advantageous.
Experience in microcontroller architecture, Cache, protocols like AHB/ AMBA,AXI, Memory(Flash, SRAM,DDR) and memory controllers
Experience and extensive hands on knowledge of HDLs (Verilog/VHDL), Scripting languages (Perl, Tcl), C/C++ for hardware modeling.
Exposure to the various Front end Integration techniques using IPXACT, CSV Scripts.
Hands on work on pre silicon validation using FPGA/Palladium would be a significant added advantage.
Experience in Low power designs with various Clock gating, DVFS techniques.
Work on Testbench and Testplan development along with the verification team. Addressing of the Analog/Mixed signal and Testability aspects of the SoC/IP along with functional requirements would be an advantage.