- 6-10 years experienced DFT engineer with good analyzing capabilities with the below skills :
Scan ion & ATPG, Boundary Scan, JTAG concepts, Scan Compression, LBIST, MBIST.
- Pattern Simulation with and without timing annotation and debugging simulation mismatches (Cadence Incisive).
- Familiarity with WGL/TDL file formats.
- Good skills in Scan compression techniques and LogicBIST.
- Exposure to Memory BIST ion tools (Preferably LogicVision MBIST).
- Good experience in Boundary Scan, JTAG concepts, Core testing using P1500.
- Should have basic understanding of Tester requirements.
- Should be good at doing synthesis and timing (RC and PT/Tempus).
- Knowledge of formal verification using LEC.
- Exposure to SoC level DFT will be a plus.
-Experience on low power DFT is an added advantage.