Responsible for the overall verification of digital logic blocks for mixed signal data communications product from architectural specification. The role encompasses developing test benches, test plans and test cases for block level, IP level and SoC level.
o Capture and analysis of design requirements o Creation of functional verification plan based on requirements
o Identification of suitable IP blocks and creates specifications for BFM / Stub development.
o IC architecture development (block architecture, interfaces, etc.) Developing a robust verification plan and environment with different methodologies
o Specification to model test bench
o Architecting layered, Class based automated test benches
o Hands - on development experience with Constrained Random test - bench using High Level Verification Languages (System Verilog / VERA preferred)
o Deploying SystemVerilog assertions (SVA) or OpenVera assertions (OVA)
o Developing and integrating verification IP
o Experiencein verification environment development using OVM / VMM / UVM
o Emulation / silicon validation experience is plus
o Strong knowledge on Perl, UNIX shell, or equivalent scripting languages
o Generating and Analyzing Code Coverage reports.
o PCIE orDDR or USB or SATA or Networking protocols work experience
o DSP experience is a plus Hands - on experience with multiple ASIC tape outs (or Spec to Release cycle) is a plus Must have excellent English written and verbal communication and interpersonal skills.