The candidate will be working for ASIC RTL design team which develops processing system SoC. As subsystem design lead he/she will lead design activities for High Speed IO sub-system. The subsystem will have SATA, USB3.0, Display Port/HDMI IPs and high-speed Serdes and multiple AXI interconnect bridges and DMAs.
The SoC integration will involve micro-arch definition, RTL design, timing constraints and design quality checks like lint/cdc. As part of design team, the candidate will own design feature/IP and will support for verification/validation of the IP/System. The ideal candidate will have excellent micro-architecture/design/timing knowledge and IP/SoC development expertise for at least one or 2 SoCs involving SATA/USB3.0. It is highly desirable that candidate has excellent verbal and written communication skills. He should be able to mentor young team member in addition to contribution as Individual contributor.
- Hands on expertise in SATA, USB3.0 protocols and design experience
- Knowledge in SATA, USB Serdes-phy integration is required
- Work experience in ARM and AXI bus based system, knowledge of memory controller required
- Must be able to create synthesis constraints based on design requirements
- Must have knowledge in clock-domain crossing(CDC, Spyglass, 0in),Linting (Spyglass) and other RTL quality checks
- Proficient in static timing analysis (primetime based). Have at least closed Prime time based timing closure for at least one SoC
- Can write sdc/tcl for DC/Primetime(PT) tool for STA analysis,
- Team player with ability to work with multisite and local teams