Staff Design Engineer - Asic/rtl/sata

Catalyst Solutions
  • Bangalore
  • 10-15 lakh
  • 7-12 years
  • Views
  • 20 Apr 2017

  • Design

  • IT/ Technology - Software/ Services
Job Description

- Hands on expertise in SATA, USB3.0 protocols and design experience

- Knowledge in SATA, USB Serdes-phy integration is required

- Work experience in ARM and AXI bus based system, knowledge of memory controller required

- Must be able to create synthesis constraints based on design requirements

- Must have knowledge in clock-domain crossing(CDC, Spyglass, 0in),Linting (Spyglass) and other RTL quality checks

- Proficient in static timing analysis (primetime based). Have at least closed Prime time based timing closure for at least one SoC

- Can write sdc/tcl for DC/Primetime(PT) tool for STA analysis,

- Team player with ability to work with multisite and local teams

Competencies/Skill sets for this job

Hands On Timing Analysis Design Experience

Job Posted By

Sudeep V
Team Integrator

About Organisation

Catalyst Solutions