a. Fundamentals of SCAN stuck-at and at-speed techniques. Expertise in handling Mentor Graphics EDT logic.
b. Knowledge on On chip clock controller (OCC). Pattern generation with Mentor Graphics TestKompress Tool.
c. Good knowledge in BSCAN operations.
d. Good Knowledge in MBIST Operations, Expertise in handling Synopsyss SMS tool sets (Integrator, Builder, Yield Accelerator)
e. Excellent track of pattern simulation and coverage analysis (preferred cadence ncsim simulator experts).
Expert in writing testbenches (Verilog, system Verilog) and tests for different
f. Experience in Asic domain,physical design domain and verification domain.
g. Good communication skils