a. Strong SV/UVM expertise, Expert level understanding of Cadence Simulator, features, Strong Digital Design Fundamentals, Strong debugging skills
b. Should be able to verify the complete SoC Top-level Integration verification, covering all corner cases
c. Coverage analysis, verification planning (vplan)
d. IMP: PCIe protocol and verification ideally should have already worked on chips with PCIe interface verification
e. Desirable: knowledge of formal verification for SoC connectivity checks
f. Experience in verliog,system verliog,VLSI.