Senior Verification Engineer

Impact HR Services Pvt.Ltd
  • Bangalore
  • 10-15 lakh
  • 5-10 years
  • Views
  • 09 May 2017

  • IT/ Information Technology

  • Electrical/ Electronics
Job Description

a. Strong SV/UVM expertise, Expert level understanding of Cadence Simulator, features, Strong Digital Design Fundamentals, Strong debugging skills
b. Should be able to verify the complete SoC Top-level Integration verification, covering all corner cases
c. Coverage analysis, verification planning (vplan)
d. IMP: PCIe protocol and verification ideally should have already worked on chips with PCIe interface verification
e. Desirable: knowledge of formal verification for SoC connectivity checks
f. Experience in verliog,system verliog,VLSI.


Competencies/Skill sets for this job

Integration Interface Verification Debugging Skills Digital Design

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Impact HR Services Pvt.Ltd