The candidate will be responsible for design and verification of high-speed and low power digital circuits using state-of-the-art IC design methodologies and flows, which include architecture specification, multi-clock domain RTL design and verification, synthesis, static timing analysis, DFT (Design for Test) and SCAN pattern generation, chip integration, and post silicon debugging. It also requires the candidate to interface with the physical design team to oversee and guide layout activities. In addition, the candidate will work as part of a larger digital design team.
- Create timing constraints and work with place & route
- Verify designs using circuit-level and behavioral-level simulations
- Supervise place & route activities
- Write circuit documentation
- Validate circuit performance in the lab.