Senior Digital Design / ASIC RTL Design Engineer - FPGA

Mississippi Consultants LLP
  • Bangalore
  • Confidential
  • 7-12 years
  • Views
  • 02 Jan 2019

  • IT/ Information Technology

  • Consumer Durables/ Semi Durables
Job Description

Role: Senior Digital Design/ASIC RTL Design Engineer/FPGA RTL Design Engineer

EXPERIENCE : 5-12yrs


- DSP fundamentals/Filter/FFT design/Data path design/Error Control Coding is COMPULSORY.
- Strong knowledge of ASIC design methodologies and flows
- At least 5-15 years of logic design and RTL coding experience with sound knowledge on verification and implementation concepts
- Minimum BE/BS degree in Electrical/Electronics/Computer science required
- Experience in physical layer ASIC architecture, micro-architecture development, design and debug
- Ability to code readable, maintainable, verifiable and synthesizable logic in Verilog and/or SystemVerilog
- Experience with lint, synthesis, CDC, STA, formality, ECO process, tool flows and scripting
- Knowledge in one or more of the following areas, a definite plus
- Ethernet (layer 2/3/4 protocols, GMII/XGMII, integration of PHY layer)
- Ability to proactively take on responsibilities and competent to work in a start-up environment
- Worked with product development companies and having seen at least a couple of tape-outs
- Experience with silicon bring-up in the lab and debugging is a definite plus
- Experience with FPGA realizations of higher complexity designs
- Ability to work with teams spread across geography with excellent communication skills

Job Posted By

Anjali Dhumane
Talent Acquisition Lead

About Organisation

Mississippi Consultants LLP