Senior Designer

  • Noida
  • Confidential
  • 3-8 years
  • Views
  • 20 Jul 2017

  • IT/ Information Technology

  • Electrical/ Electronics
Job Description

Our team (High Speed Interface) develops IP for data transmission on wired networks. In particular, we design (from specification to validation) macros capable to transmit and to receive data signals up to 56Gbps (current project) to be embedded in many SoC. DMA division, in tight contact with customers, develops ASICs that include our macros to manage several data transfers in networking applications.
Pad Ring Definition / Pin assignment, Floorplanning and Block Placement
Cell Placement, Clock Tree Synthesis, Routing
Full chip assembly and integration
Layout Extraction, Back Annotation and Delay Calculation
Layout Verification (DRC/LVS/DFM), EM checking, Power Analysis
Timing Closure at subchip and full-chip level ECO timing loops
Chip Finishing (FEOL tiles / BEOL tile / Embedded metrology)

Verilog/VHDL basic language
Knowledge on CAD tools for ASIC layout design, verification, floorplanning and timing analysis from vendors such as Synopsys, Cadence, Mentor Graphics are a must for this position:
Cadence Innovus, Synopsys ICC2
Mentor Calibre
Synopsys Design Compiler, Synopsys PrimeTime, Synopsys Formality
Cadence Tempus
Linux operating system, cshell and tcl language

Basic knowledge on DFT tools as following ones:
o Synopsys Test Compiler, Synopsys DFT Compiler, Synopsys Tetramax

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