This team is responsible for the architecture and implementation of advanced DFT/DFD/DFM (design for test/debug/manufacturability) techniques for high performance, highly integrated SoCs. Candidates selected will be directly involved with implementation of various DFT architectures to achieve high quality manufacturing tests that reduce test cost, and increase production quality. In addition, candidates selected will also be involved in all aspects of DFT including architecture, methodology development, design, vector development, manufacturing testing, and debug.
Responsible to implement complete design testability cycle from architecture to silicon testing.
To ensure adherence to corporate and automotive Testability targets by defining, planning and executing complete flow of DFT, ensuring high coverage, complete Testability, support to failure analysis and Silicon support to reach Maturity targets
Good RTL(VHDL or Verilog or system verilog) writing skills and/or the ability to use industry standard tools like Tetramax, TestKompress , Design Compiler, etc.
Clear concept about scan based design.
Knowledge on ATPG and different Fault Models (SA, Transition, Iddq , SDD etc)
Coverage improvement techniques
SOC integration and RTL modification as per DFT requirement.
Knowledge of Boundary Scan Testing and testing of ips viz ADC, FLASH , PMU in standalone mode
Basic knowledge of following :synthesis constraints , ATE ,Silicon defects and its logical effects
Awareness of Latest technique viz. Lowpower ATPG, Analog Bist, Logic Bist would be appreciated and preferred.
Adaptable, Flexible, creative and capable of working independently as well as a team player. Should have a strong sense of urgency.
Solutions orientation; Quality driven; Execution minded; Customer focused