Senior ASIC Design Engineer - STA

Best InfoSystems Ltd.
  • Bangalore
  • 13-14 lakh
  • 10-15 years
  • Views
  • 05 Jul 2017

  • IT/ Information Technology

  • IT/ Technology - Software/ Services
Job Description

- Complete understanding of Syn/STA concepts (Synthesis, Timing, Equivalence Checks, Extraction, Noise, Power, UPF/CPF) and various flow

- Should be able to independently handle Synthesis/STA (timing/noise/power) . QOR, Budgeting, SDC for PD and STA signoff closure at full chip level

- Understand IP test requirements, implement/ Verify. Verilog coding for synthesis and testbenches

- Test mode timing support/debug and closure at full chip level

- Handle post-silicon pattern generation, Validation and ATE debug/support

- Understanding Test/DFT modes SDC

- Complete familiarity/exposure of tools used in DFT implementation (DC/RC, Tk/Tmax, Virage/Mentor memory BIST, Mentor Bscan)

- Should have ability to debug tool /design issues. Low ATPG coverage etc

- Familiarity with STA. DFT mode constraints generation. Help STA team in closure for DFT modes

- Good scripting skills (TCL/Perl)

- Debug any issues in implementation and verification and resolve to closure

- Interact with DM/Lead, STA /PD team to communicate work progress or resolve cross function issues

- Interact with tool vendors and debug tool related or IP related issues independently

- Independently debug any issues in implementation and verification and be able to help other team mebers

- Provide feedback to FM on problems/issues in flow and help contribute to methodology improvements

Competencies/Skill sets for this job

Coding Scripting Asic Design Verification Sdc

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About Organisation

Best InfoSystems Ltd.