Exposure to Synthesis, static timing analysis (STA) and timing sign-off ? experience with: o Low power design techniques and checks o Logical equivalence checks (in Formailty or LEC)
Should have good timing concepts and able to close timing of Block/SoC independently.
Should have hands on experience in constraint generation
Hands on experience in Logical synthesis like Design compiler/ Rc compiler
Knowledge in Formal Verification. Comfortable with LEC/formality tools
Should able to generate and implement functional Ecos
Should have experience in Pre-layout and Post layout timing analysis in tools
Should have experience in two industry standard tools like Primetime/ETS
Hands on experience in crosstalk timing closure.
Knowledge in Path based analysis, AOCV, DMSA is a plus.
Knowledge in complete physical Design flow is a plus.