Key responsibilities involve:
System Verilog – SV (Mandatory).
Hands on experience in UVM methodology.
Basic knowledge of scripting
Good experience in ASIC Verification (Using System Verilog / Verilog)
Experience on development of test bench, writing test cases, debugging the RTL
Processor/ARM Based SoC Verification
Advantage to have experience in gigabit Ethernet protocol or any other protocols work in gigabit
Expected to have good practical understanding of technology, its application and be involved in implementation, debugging and documentation
Should be self motivated, able to work in a team and lead the junior engineers
Willing to travel abroad