The ideal candidate will have 10+ years of physical design experience, with recent successful tapeouts in deep submicron technologies (45nm and below).
- Strong knowledge of Timing Analysis and Flow.
- Proven ability to handle team with respect to STA.
- Proven ability to execute to stringent schedule and Strong communication skills with following responsibilities,
- Work independently and with multisite teams in the areas of RTL to GDSII implementation with focus on STA Methodology, flow and implementation.
- Well versed with Synthesis, partitioning, IO Planning, constraints validation, timing budget generation, Full Chip Signoff STA, Block Level Signoff STA, pre-and-post Layout timing closure, Place and Route.
- Interact with various team comprising of block build, Design automation(CAD) and design technology teams to resolve various issues in timely manner.
- You will also be responsible for driving methodology development, automation, collaborate with other design teams, share best practices followed.
- Experienced in Synopsys PT-PTSI or EDS (Timing Encounter) tools used and their capabilities & underlying algorithms
- Sound expertise in Tcl, Perl, Shell scripting
- Needs to work from customer site in the US during requirements of Project kick off, mid reviews and hand over.
- Synopsys ICC, PT-PTSI, DC, OR EDS/ SoCEncounter
- Taking care of full chip SOC PD issues (including Timing budget, constraint development, Flow development, Timing sign off, at 65, 45, 28nm and below.
Soft Skills :
- This job involves working from customer site.
- Highly motivated technical person who wants to grow experience building large ASIC and exposure to work with multi-site team.