RTL Design Engineer

  • Bangalore
  • 10-15 lakh
  • 4-8 years
  • Views
  • 24 Apr 2017

  • IT/ Information Technology

  • Recruitment/ Staffing
Job Description

- You will be responsible for IP / sub-system level micro-architecture development and RTL coding.

- Prepare block/sub-system level timing constraints.

- Integrate IP/sub-system.

- Perform basic verification either in IP Verification environment or FPGA.

- Experience in Logic design / micro-architecture / RTL coding is a must.

- Expertise in Verilog is a must.

- Should have knowledge of AMBA protocols - AXI, AHB, APB.

- Experience in Synthesis / Understanding of timing concepts for ASIC or experience in Xilinx FPGA Design Implementation is required.

- Experience in design of DDR / USB / PCIe controller or such complex protocols is a plus.

- Hands on experience in Multi Clock designs, Asynchronous interface is a must.

- Experience on tools utilized in all phases of ASIC development such as Lint, CDC, Simulation etc. is required.

- Knowledge of low power concepts and experience is a plus. ,

Competencies/Skill sets for this job

Logic Design Hands On Coding Rtl Cdc

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