1. Verification of chip level functionality (mainly connectivity, programmability, power up/down, mode control, reset).
2. Negotiating and executing functional verification plans.
3. Writing/debugging/maintaining behavioral models, monitors, and self-checking test benches.
4. Logging bugs and tracking verification results.
5. Delivering status reports and verification reviews.
6. Generating and maintaining verification schedules.
1. At least 5 years of experience doing functional verification, preferably of mixed signal designs
2. Solid working knowledge of Verilog.
3. Basic understanding of switching and linear regulators and/or mixed-signal designs
4. Experience writing behavioral models of analog blocks, preferably for event driven simulators.
5. Experience writing self-checking test benches.
6. Experience writing assertions and monitors of analog signals.
7. Solid working knowledge of the Cadence AMS designer and net listing.