Objective & Main Duties of Job:
- As a Post Silicon Validation engineer you will be responsible for bring up, post-silicon validation & debug of Invecas IP products which include Standard cells, PLL, ADC/DAC, DDR PHY, SERDES, MIPI PHY.
- The IP will be taped out to the target foundry as independent test chips and you are expected to perform the complete IP validation and generate the Silicon report.
- Expected to work as part of a team with Digital designers, Analog circuit design, Architects & Board engineers to ensure successful IP Validation and Characterization with aggressive deployment cycles.
- Independently own and Drive the validation closure as per the required standards.
Experience, Skills Required:
- Well versed in the usage of electrical measurement tools such as oscilloscopes and logic analyzer
- Operation of Advanced Bit Error Rate Testers (BERT), Protocol Analyzers and power measurement equipment is a plus
- Good understanding on any one of IP signalling/protocol
- Hands on knowledge and experience in Validation and debug of Analog Mixed Signal IP for any one protocol
I2C, UART, USB, PCIe, etc.
- Development and documentation of silicon test plans and guidelines
- Perform IP Test chip bring-up, timing characterization and validation as per plans
- Perform signal measurements and protocol checking on interface to make sure designs are meeting all required specifications
- Perform tuning for system stability, performance and power optimization
- Perform regression and interoperability testing as per relevant standards across process, voltage and temperatures
- Debug Test chip and board issues related to logic, circuit design & signal integrity
- Work closely with R&D Engineering teams to resolve issues in time critical environment
- Provide detailed silicon debug and issue characterization to help provide clear and accurate direction of the debug effort.