Power planning, optimization, power grid and signal routing considering timing constraints.
Design floor planning, analogue and memory macro placement.
Place and route including timing closure.
Extraction of layout parasitics and SPEF/ SDF generation. Signal integrity tests.
Post-synthesis static timing analysis (STA) and post-layout STA.
Physical verification (DRC, ERC, LVS, ANTENNA rules).
Writing, running, optimization of scripts for above tasks.
Implement and monitor Quality Assurance/ Quality Control standards based on corporate guidelines in a project setting.
Have done multiple tape outs and proven record of designing complex ICs in state of the art CMOS process technologies and has successfully placed products into volume production, preferably multiple times.