Engineer would be responsible for doing Physical Design implementation , Timing Closure and Physical Verification at Block Level.
Expertise in 7nm / 14nm / 16nm / 28nm
Should execute block level floor planning , PG Planning , partitioning , placement , scan - chain - reordering , clock tree synthesis , timing optimization , SI aware routing , timing analysis / closure and ECO tasks (timing and functional ECOs) , SI closure , design rule checks (DRC) , and Logical vs. Schematic (LVS) checks , Antenna checks , IR Drop , STA , Power and noise analysis.
Candidate should independently able to close STA timing across all corners and modes for blocks and should be able to generate ECO independently .
Candidate should understand all aspects of timing closure across many corners .
Experience / Knowledge in Chip level Timing closure & Physical Design activities is preferred
Experience in Physical Design Implementation on advanced technology nodes like 28nm , 20nm , 16nm , 14nm & 7nm for block level implementation.
Good communication skills are a MUST Thanks