Implementation of multimillion gate SoC designs in cutting edge process technologies
Strong expertise of physical design including Synthesis, Floor Planning, Power Plan, Integrated Package and Floorplan design etc
Proficient in physical design methodology at HM and or top level Floor planning, place and route, CTS, STA and PV closure.
Work with design teams for closing CTS, IO timing, DFT timing.
Should have knowledge of clock tree synthesis, low power techniques, Timing analysis.
Good understanding of physical design flows, flow automation and design data management.
Good software skills (Perl, TCL, shell scripts) - good overall scripting knowledge and hands-on experience.
Good customer support skills across remote sites.