• More than 3+ years of relevant experience as a Physical Design Engineer.
• Candidate will be responsible for full-chip SoC Physical Design flows
• Experience with latest industry-standard deep-submicron Automated Place and Route (APR) and Physical Verification (PV) flows and tools required
• Must have demonstrated success taping out full-chip SoCs
• Solid Verilog skills expected
• Knowledge of synthesis, STA and DFT flows a plus
• Proficient with automating design flows using Perl, TCL, and Make.