Computer Power Group Inc
  • Bangalore
  • 10-15 lakh
  • 5-10 years
  • Views
  • 16 Jan 2017

  • IT/ Information Technology

  • IT/ Technology - Software/ Services
Job Description

To Perform highly optimized Auto Place and Route(APR), chip level layout integration and chip level verification of PIC Micro controllersFloor planning and Place and Route at block level and chip level Custom Clock Tree / Clock Tree Synthesis (CTS) methodology development Integration of Custom and Digital blocks Active participation in STA by identifying and executing timing ECOsExecute tape out sign off checks (LVS, DRC, EMIR, DFM, Signal&-EM) Interact with the CAD team to ensure coordination on layout related tools/libraries/scripts for cost&-effective and timely release Interface with Design Engrs to provide feedback and implement enhancements to ensure design correctness and robustness.RequirementsB.E/B.Tech or MS in Electronics or Electrical Engineering Expert user of Synopses ICC Floor&-Planning, Place and Route and Clock Tree Synthesis Good verbal/written communication skills with local and remote teams Experience in Micro controllers or related physical designs on 65/40nm and below Strong debugging skills including STA, CTS and Physical verification Good experience RC Extraction, Signal Integrity, IR drop analysis and Crosstalk analysis Good at scripting in TCL, PERL etc.

Competencies/Skill sets for this job

Ir Drop Analysis Physical Design Signal Integrity Cad

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Computer Power Group Inc