Manager/senior Manager - FE Integration & Implementation (14-17 yrs)

Talpro
  • Bangalore, Hyderabad
  • 15-30 lakh
  • 14-17 years
  • Views
  • 16 Jan 2017

  • IT/ Information Technology

  • IT/ Technology - Software/ Services
Job Description

- At least 14+ years experience in complex ASIC Design. Direct experience in SOC or Graphics/Video is plus.
- Have in depth knowledge of entire design process from Design specification, defining architecture, micro-architecture, RTL design and functional verification, synthesis, Physical Design, Timing closure, Tape-out, and post-Si debug.
- Have hands-on experience in Chiplevel Design/Integration activities.
- Some Physical Design exposure required.
- Should be able to Lead a team, and provide Technical mentoring and guidance to junior engineers.
- Perform Synthesis and netlisting tasks such as SDC Development, Scan Insertion, ECO implementation, Formal Verification, etc.
- Some exposure to DFT is a strong plus.
- Work with Physical Design team on Floor Plan, budgeting, timing closure, Signal Integrity, ECO flows, Power analysis, IO PAD placement, etc.
- Should have expertise in : Cadence RTL Compiler, Design Compiler, PrimeTime, Conformal LEC. Good knowledge of datapath compilers is required.
- Should have proficiency in flow development and scripting.
- Expertise in Perl and Tcl is a must.
- Should be able to work closely with RTL Designers and Backend Physical Design teams across multiple sites.
- Must have good communication & Analytical thinking skills.
- Knowledge of chip bus interfaces such as AHB and various standard peripherals & interfaces is a plus.
- Bachelor/Master/ Degree in Electrical or Computer Engineering


Competencies/Skill sets for this job

Perl Verification Physical Design Asic Design

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Talpro