To lead a team of PD engineers to successfully tapeout multiple chips / SoCs at differentprocess nodes for different product groups. Responsiblefor independent planning and execution of RTL - to - GDSII of SOC and full chipdesign.
Hands on experience in leading top level of PD of chips including IO, Bump Maps, Powergrid.
Experience on full - chip, Timing closure & Physical Design activities.
Based onexperience, this position may be considered for a leadership role in thecompany.
Work independently and with multisite teams in the areas of RTL to GDSIIimplementation.
Well versedwith Synthesis, constraints validation, Full Chip Floor planning, partitioning,timing budget generation, power planning, IR / EM Drop Flows, Full Chip SignoffSTA, Block Level Signoff STA, Place and Route, and Physical VerificationDRC / LVS / ERC, DFM. Proficientin Synopsys ICC or Cadence Encounter.
Would beinvolved in setting up the flows, automation and scripting with Perl or TCL. RTL designexperience is a plus
Working knowledge of Lynx flow from Synopsys is a plus Experiencewith various process nodes (TSMC 28 - 65, IBM, Tower / Jazz) is a plus Experiencewith multiple chip tapeouts through full Physical Design flow