Lead Implementation Engineer-Physical Design

Roland & Associates
  • Bangalore
  • 15-20 lakh
  • 10-18 years
  • Views
  • 25 Apr 2017

  • IT/ Information Technology

  • Electrical/ Electronics
Job Description

Physical Design.
Experienced in deep submicron effects and low power implementation using UPF/CPF.
knowledge in Perl and TCL.
Cadence implementation tools (Genus, Innovus, Tempus) and Calibre physical verification for DRC/LVS.
Be responsible for Timing constraint development, Synthesis, DFT, generation/optimization of pad rings, full chip floor-planning and partitioning with power domains, clock tree synthesis, power and IR drop analysis and final timing closure.
Be responsible for Power-aware implementation flow, including UPF/CPF and verification using Conformal Low Power.

Competencies/Skill sets for this job

Synthesis Perl Pad Closure Deep Submicron Rings

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Roland & Associates