Lead ASIC Design Engineer/chip Lead - Synthesis/rtl

Catalyst
  • Bangalore
  • Confidential
  • 4-10 years
  • Views
  • 09 Feb 2017

  • IT/ Information Technology

  • IT/ Technology - Software/ Services
Job Description

- Define and architect high-performance blocks for the latest, most advanced networking ASICs

- Responsible for micro-architecture, RTL implementation, logic synthesis and timing analysis.

- Work with verification team in validating the design and architecture choices.

- Work with physical design and signal integrity teams to achieve timing closure.

- File patents and participate in patent reviews.


Job Posted By

Sudeep V Iyer
Gardenar - Success Enablement

About Organisation

Catalyst