Lead ASIC Design Engineer- Synthesis/rtl

Catalyst Solutions
  • Bangalore
  • 15-20 lakh
  • 10-16 years
  • Views
  • 20 Apr 2017

  • IT/ Information Technology

  • IT/ Technology - Software/ Services
Job Description

- Define and architect high-performance blocks for the latest, most advanced networking ASICs

- Responsible for micro-architecture, RTL implementation, logic synthesis and timing analysis.

- Work with verification team in validating the design and architecture choices.

- Work with physical design and signal integrity teams to achieve timing closure.

- File patents and participate in patent reviews.

- Experience in networking ASIC architecture and design, from routing, switching, to security.

- Expertise in packet processing, lookup & scheduler engine, hashing and deep packet-inspection.

- Experience in memory technologies such as DDR3/4, GDDR, and HMC or HBM.

- Experience with EDA tools such as Synopsys Primetime, Cadence Conformal, Atrenta CDC, or formal verification is a plus.

- Experience with security algorithms such as AES-GCM, hash functions such as SHA, MACsec standard (IEEE 802.1AE) and protocols such as IPsec.

-Familiar with 10G/25G/ 100G/400G Ethernet, Interlaken, 802.11, OTN and other standards.

- Above experience is not a must for candidature but good to have .

Competencies/Skill sets for this job

Networking Processing Physical Design Timing Analysis

Job Posted By

Sudeep V
Team Integrator

About Organisation

Catalyst Solutions