Work experience on IP/SOC level verification.
Proficient knowledge on System Verilog
Methodology like VMM/OVM/UVM is must.
Should have good communication and Leadership skils.
Work experience on Intel IOSF protocol is advantage.
Proficient knowledge in developing Testplan is must.
Work experience on developing Testbench at IP/Subsytem level is mandatory.
Develop design standards and guidelines to ensure quality and performance.
Prepare design verification plan based on design specifications.
Plan and schedule assigned projects for timely completion.
Excellent Communication skills