Design Verification Engineer - System Verilog

  • Bangalore, Hyderabad
  • 10-15 lakh
  • 5-10 years
  • Views
  • 12 Dec 2016

  • IT/ Information Technology

  • IT/ Technology - Software/ Services
Job Description


- B.E/M.E/M.Tech or B.S/M.S in EE/ECE with at least 12+ years of relevant experience in IP and SOC verification

- Proven experience of architecting testbench from scratch and did hands on implementation of the same.

- Proven end to end verification of complex IP using system verilog and any of latest methodologies which include UVM, OVM, VMM

- Strong domain knowledge of latest ARM based interfaces which include AXI Memory Map and AXI streaming and high Speed serial connectivity, etc.

- Proficient knowledge of system verilog, HVL based methodology (UVM or OVM) and hands on scripting experience for automation using perl

- Proven debugging skills to root cause system level performance issues and customer functional issues to IP level scenarios and recreate the same in functional verification environments.

- Understanding and experience in verification of ARM based Interconnect, DMA controllers will be an added advantage

- Having System level knowledge / Verifying IP at system level and prior working knowledge of the Xilinx implementation tools will be a definite plus

- Self-driven, motivated, results oriented individual with superior academic achievements

- Excellent interpersonal, written, group communication and problem solving skills

- Good organizational and execution skills with ability to multi-task, prioritize

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