DFT Engineer to work on DFT activities of SoC/IP Macros
Perform Scan Insertion, Scan compression, MBIST insertion, memory repair, Simulation, synthesis, timing analysis, lint check, clock domain crossing check, conformal low power check, and formal verification.
Work closely with design team to close IP block specification/DFT requirement.
Work closely with physical design team to ensure quality DFT implementation.
Work closely with SIM team to hand off ATPG setup and enable ATPG pattern generation, timing simulation and support silicon bring up.
Bachelors or Master with 3-10 years of experience in DFT (Design for Testability), Design for test (DFT) techniques and structural tests such as Scan/ATPG, and JTAG Insertion, Scan Compression, Scan Simulation Fault modeling: Stuck-at, Transition, Path Delay, Gate-Exhaustive, IDDQ etc. Memory BIST techniques; memory repair; MBIST tools. ATPG pattern generation, timing simulation, Silicon bring up experience is plus Yield optimization; Test Time Reduction techniques Perl, Python, for Scripting