Looking for candidates with good experience in DFT, SCAN stuck - at and at - Speed techniques, BIST, ATPG and ATE (Automated Test Equipment). Position Summary: Job Title: DFT Engineer Joining Period: Immediate / 15 Days / Within 30 - 60 Days Job Description: Must Have: * SCAN stuck-at and at-speed techniques. * Fundamentals of SCAN stuck-at and at-speed techniques. * Expertise in handling Mentor Graphics EDT logic. * Knowledge on Onchip clock controller (OCC). * Pattern generation with Mentor Graphics Test Kompress Tool. * Good knowledge in BSCAN operations. Knowledge in MBIST Operations. * Expertise in handling Synopsys SMS tool sets (Integrator, Builder, Yield Accelerator). * Excellent track of pattern simulation and coverage analysis (preferred cadence NCSim simulator expert Experience in ATPG, Scan, BIST and Mentor Test Kompress. * Expert in writing test benches (Verilog, system Verilog) and tests for different components like PLL, ADC etc for generating ATE vectors. * Experienced engineers with DFT flow, ATPG, Scan, BIST and Mentor Test Kompress. * Experience with the mentor tool sets. * Familiarity with scan, mem bist, jtag concepts and 3rd party tools. * Tester program creation, debug, and validation of DFT features on ATE.