Need knowledge of design for test (DFT) structures such as scan chains, scan compression and verification concepts for test coverage (ATPG). Be able to generate ATPG and analyze coverage results and how to extend or optimize them. Need to know how to run gate simulation for to verify scan patterns to demonstrate functionality.
2 years’ experience in DFT in ASICs
experience in DFT for large scale ASICs. Experience with Mentor Graphics DFT tools.