The incumbent will be involved in design Implementation (Netlist2GDSII flow) of products related to Engine control , Safety(including airbag) , Body, Chassis and Advanced Driver Assistance System(ADAS) for futuristic cars from the stable of leading car manufacturers ( Eg-Daimler,-Benz, BMW, VOLVO)
Involved in all aspects of Chip and IP implementation from RTL to GDS - including DC Synthesis, Floor planning and Power Planning and Analysis, Place & Route, Timing closure, Physical Verification, Formal verification and Power analysis.
Apart from the obvious challenge of reducing Area, mask re spin, consumption and increasing performance, other challenges include complying to ASIL-D safety standard, striving for zero PPM, crypto subsystem leveraging e-Flash etc
Knowledge of full RTL to GDSII flow ( Synthesis, STA, Floorplan, CTS, PnR, DRC/LVS, SI, IR Drop )
Hands-on experience with synopsys and Cadence PnR tools, Floorplanning, IR Drop and Physical verification
Should have good understanding of verilog/VHDL
Exposure to low power techniques
Knowledge of tcl and perl scripting is a must
Adaptable, Flexible, Global Approach/Synthesis, creative and capable of working independently as well as a team player. Should have a strong sense of urgency.
Solutions orientation; Quality driven; Execution minded; Customer focused