Having worked on CMOS process technologies in 14nm is an added advantage.
- Experience of mixed signal layouts- DAC/ADC/PLL/TX/RX/LDO's, Regulators, Amplifiers etc
- Layout Design & Verification of custom and analog blocks following the design rules & guidelines, Layout Verification, Error Analysis and FixesCell layout design, floor planning, Signal and Power routing, porting
- Design the Layout to meet the ESD & Latch up Rules, and fix errors based on the checks provided - run tools, analyze errors and fix them
- Design Layout to Meet Reliability requirement to meet RV Checks (including: IR Drop, EM, SH, I peak etc..)
- Work independently on Analog layout design of block level and chip level from schematics
- Candidate should be able to handle project independently and estimate efforts for work.
- Hands on experience of FINFET Technology
- Knowledge on Scripting and Automate Layout / Verification Flows and Task