Hands on experience in Analog Layout design of various designs Linear and Switching regulators, SerDes, LVDS, DDR Phy, PLL and analog building blocks amplifiers, comparator, oscillator, voltage, current reference circuits etc.
Understanding of different layout concepts like matching, shielding etc.
Should have prior work experience in CMOS process technologies - 22nm, 28nm, 45nm, 65nm etc.
Hands on experience in FINFET technology will be an added advantage
Good understanding of deep sub-micron and DFM issues.
Thorough working knowledge of layout design and physical verification tools using Cadence Virtuoso layout suite, Mentor Calibre, Synopsys Hercules etc.
Scripting knowledge of perl & cadence SKILL will be added advantage.