Must have executed at-least 1 ASIC/SoC Verification project entirely At-least 4 years of experience in System Verilog HVL. At-least 3 year of experience in OVM/UVM/VMM/Test Harness. Hands on experience of developing assertion, checkers, coverage and scenario creation. Experience in developing test and coverage plan, Verification environment and validation plan. Knowledge of atleast one industry standard protocols like Ethernet, PCIe, MIPI, USB or similar isrequired.