Candidate will be involved in developing Testbench for the Block / Cluster, Test cases, Tesplans and Functional and Code coverage closure activities and reviews of documents and code.
Candidate will be individually responsible for successful delivery to clients for given tasks/module of Testbench/Testcases.Candidate will responsible for the Client Support activities which conference call on reviews and Bug closure.
At-least 1.5 years of experience in System Verilog HVL.At-least 1 year of experience in OVM/UVM/VMM/Test Harness.
Experience in developing test and coverage plan and Verification environment.
Knowledge of industry standard protocols like Ethernet, PCIe, MIPI, AXI-AHB Bus etc. will be added advantage.