Key Performance Competencies
Quality of Work
Essential Duties and Responsibilities
Responsible for bring out the rules for the FPGA IO and IP pin allocation. Should be able to understand the IP design rules for a given FPGA family and frame the constraints out of it.
Coordination with development in the process of implementation of FPGA support in FSP.
Responsible for creating the FPGA libraries for FSP.
Responsible for validating the rules implemented by the development team.
Have good knowledge in FPGA IO and IP pin allocation rules.
Have experience in pin planning in any of the FPGA tools like Vivado,Quartus, Libero.
Good experience in Perl, TCL scripting languages.
Minimum 3+ years of experience